1. Field of the Invention
The present invention generally relates to packet data processing apparatuses and packet relay apparatuses, and more particularly to the packet data processing apparatus and the packet relay apparatus using the packet data processing apparatus which is mutually connected to terminals through communication networks and which execute a packet process including a destination table searching process and a header replacing process.
2. Description of the Related Art
Recently, a communication network between terminals has been extended widely. And it is more required to link networks, for example, to mutually connect several LANs (Local Area Networks) or connect a LAN with a dedicated line, in order to extend a size of networks. Current network architecture is an IP (Internet Protocol) network. The IP is a connectionless network protocol corresponding to a network layer of an OSI (Open Systems Interconnection) reference model of the ISO (International Organization for Standardization). While a connection network protocol predetermines a communication path between terminals, a packet relay apparatus mutually connecting between LANs establishes a communication path by forwarding a packet storing communication data toward a destination in a connectionless IP network. In a relay process of the IP network, a packet process such as a destination table searching process or a header replacing process is required.
The packet process in the IP network is required to operate a checksum for a packet header, search the destination table and replace the packet header in order to relay the packet and is also required to perform a packet filtering. Conventionally, entire packet processing is executed by software since the entire packet process is too complicate to be conducted by hardware.
FIG. 1 is a diagram showing a configuration of a conventional packet relay apparatus executing the packet process by a processor. In the conventional configuration in which a processor 10 connects to a memory 11 via a bus 12 as shown in FIG. 1, the conventional packet relay apparatus executes the packet process by the processor 10 storing a packet in the memory 11 and processing the packet.
The conventional packet relay apparatus 14 shown in FIG. 2 includes the processor 10 and the memory 11 in FIG. 1. In order to forward a packet, the packet relay apparatus 14 receives the packet by a receiving interface 15 and then stores the received packet in the memory 11 temporarily. The processor 10 sends a switch fabric 16, the received packet and information which is determined as destination information and to be attached to the received packet after the processor 10 performs the checksum, searches the destination table and replaces the packet header for the received packet during the packet process.
In the packet relay apparatus 14, the packet is sent from the switch fabric 16 to a proper one of transmission interfaces 17 based on determined destination information. The packet is transmitted from the transmission interface 17. In this manner, the conventional packet relay apparatus 14 forwards the packet to the destination.
In the packet process in the packet relay apparatus, the processor 10 in FIG. 1 stores the received packet data temporarily in the memory 11 and then transfers portions of the packet data stored, which are required in accordance with instructions of a program, to a general purpose register 21. Subsequently, the processor 10 performs the packet header checksum, searches the destination table and replaces a destination address in the packet header for the packet data stored in the general purpose register 21 in accordance with an instruction order. Then, the processor 10 stores the packet data in the general purpose register 21 when it is required. After the packet data are processed, the processor 10 retrieves the packet data from the memory 11.
Referring to FIG. 1, the processor 10, which is used for the packet process including the packet header checksum, the destination table search and the destination address replacement, generally includes the general purpose register 21, for example, a single set of registers r0 to r7, to maintain data to be operated or an operation result, selectors provided with the general purpose register 21 to output and input data, an operation part 22 to execute data transmission, a comparison or an arithmetic operation based on an instruction, a controller 23 to read the instruction and send a control signal to each component provided in the processor 10, a program counter 24 to maintain a program pointer of the current executing instruction, a flag register 25 to evaluate the operation result, an external bus interface 26 and an external bus buffer 27. The processor 10 executes the packet process by conducting the above components based on the instruction that is externally read.
However, recently, higher speeds and larger amounts of data in data transactions are increasingly required by networks. Also, it is desired to improve the speed of the packet relaying process. Therefore, a special hardware circuit for the packet process has been developed and mounted in the packet relay apparatus because the packet process by software using the processor does not achieve a sufficient performance. However, it is not easy to modify the special hardware circuit in order to carry out a revised protocol or improve a service provided through a network. Disadvantageously, it is needed to newly develop another special hardware circuit each time the protocol is revised or the network service is improved.
On the contrary, the packet process conducted by the processor, which is executed by the instruction (that is, software) in the manner mentioned above, is flexible to be modified in order to carry out the revised protocol and to improve network service after mounting on the packet relay apparatus.
The conventional packet process, which has a high flexibility of modification, is conducted by the processor 10, the memory 11 and circuits being connected to the processor 10 and the memory 11 by the bus 12. The processor 10 transmits the packet data between the processor 10 and memory 11.
However, in the conventional packet process by the processor 10, the packet data temporarily stored in the memory 11 is read out or written on the memory 11. Disadvantageously, it is difficult to carry out a high speed of the packet process.
That is, in the conventional packet process of the processor 10, the packet data are stored in the memory 11. The processor 10 retrieves the packet data when the packet data are needed, and processes the packet data based on contents of the packet data. Then, the processor 10 writes the packet data and the process result in the memory 11. The processor 10 indicates a read-out address to the memory 11 and then reads out data from the memory 11. Similarly, the processor 11 indicates a write address to the memory 11 and then writes data to the memory 11. In this case, compared with a cycle time of the processor 10, it takes much time for the processor 10 to indicate an address to the memory 11 through to complete reading out or writing data from/to the memory 11.
In a sequential execution type of a processor, only a single process can be executed. Thus, a reading operation and a writing operation can not be carried out at the same time. In addition to the above disadvantage, it is difficult to develop a memory circuit that can realize to read out data and simultaneously write data. Generally, it is impossible for the processor to read out data from and write data to the memory at the same time. The above inconvenient operations for the reading process and the writing process to the memory prevent the processor from transmitting data to or from the memory at a high speed.